Method and device for converting a quantized digital value

ABSTRACT

The invention concerns a method and a device for converting an input digital value quantized in accordance with a first quantization factor and encoded on at most n1 bits, into an output digital value quantized in accordance with a second quantization factor and encoded on at most n2 bits. The method comprises the steps of: multiplying the input digital value by an integer B, encoded on at most β bits, so as to generate an intermediate digital value; and dividing, in fixed point, the first intermediate digital value by the number 2 α , where α is an integer not greater than n1+β, generating the output digital value. The number B/2 α  is substantially equal to the ratio of the second quantization factor over the first quantization factor. Additionally, the divider means comprise a Sigma-Delta modulator.

[0001] The present invention relates to the field of fixed-point digitalsignal processing. Applications may be found for it in any fixed-pointdigital system, and particularly in the digitally modulated synthesizersused in the radio transmitters and the radio transceivers of a digitalradiocommunication system.

[0002] For carrying out operations on binary numbers, a floating-pointdigital system comprises software resources such as a correctlyprogrammed DSP (Digital Signal Processor). A fixed-point system,however, only comprises sequential logic circuits such as digitaladders, digital multipliers, shift registers or the like.

[0003] The binary numbers which are processed by a fixed-point digitalsystem encode quantized values corresponding to a real value X (forexample the variable value of the radio signal received by a radioreceiver, or the constant value of the frequency of a radio channel).These quantized numbers are represented by integers between zero and2^(n)−1—where n is the number of bits used for encoding theinformation—if the value X is always positive, or between −(2^(n)−1) and2^(n)−1 if the value X is signed (that is, if it can be negative). Byconvention, Xq denotes the quantized value which is obtained from thereal value X by a quantizing operation. For linear quantizing, thecorrespondence between the real value X (so-called real information) andthe quantized value Xq (so-called quantized information) is given by therelation:

Xq=round(X×Cq)   (1)

[0004] where Cq is a real number referred to as the quantizationcoefficient.

[0005] The quantization of the system is determined by the number Cq inrelation with the number n. The quantization coefficient Cq is suchthat: $\begin{matrix}\left\{ \begin{matrix}{{{{round}\quad \left( \left| {X(t)} \middle| {\times {Cq}} \right. \right)} \leq {2^{n - 1} - 1}},{\forall t},{{if}\quad {the}\quad {information}\quad X\quad {is}\quad {signed}}} \\{{{{round}\quad \left( {{X(t)} \times {Cq}} \right)} \leq {2^{n} - 1}},{\forall t},{otherwise}}\end{matrix} \right. & (2)\end{matrix}$

[0006] where |x| denotes the absolute value operator of the realvariable x.

[0007] The act of quantizing the information X creates an error,referred to as the quantization error and denoted by e, such that:$\begin{matrix}{e = {{X - \frac{Xq}{Cq}} = {X - \frac{{round}\left( {X \times {Cq}} \right)}{Cq}}}} & (3)\end{matrix}$

[0008] The error e is of course variable, inasmuch as it depends on thevalue X. According to the properties of the rounding function, the errore is always such that ${e} \leq {\frac{1}{2 \times {Cq}}.}$

[0009] The maximum value of the quantization error, denoted by e_(max),is therefore given by: $\begin{matrix}{e_{\max} = \frac{1}{2 \times {Cq}}} & (4)\end{matrix}$

[0010] The inverse of the quantization coefficient Cq is the resolutionof the digital system, that is to say the smallest variation of the realinformation which is distinguishable in the quantized information. Putanother way, $\frac{1}{Cq}$

[0011] is such that if $X = {\frac{1}{Cq} + X^{\prime}}$

[0012] then Xq=1+Xq′.

[0013] Optimization of the dynamic range of the system generally leadsto the quantization being defined by choosing Cq such that:$\begin{matrix}\left\{ \begin{matrix}{{{Cq} = \frac{\max \left( \left| {X(t)} \right| \right)}{2^{n - 1} - 1}},{\forall t},{{if}\quad {the}\quad {information}\quad X\quad {is}\quad {signed}}} \\{{{Cq} = \frac{\max \left( {X(t)} \right)}{2^{n} - 1}},{\forall t},{otherwise}}\end{matrix} \right. & (5)\end{matrix}$

[0014] Certain systems dictate the quantization of the digital data, forexample in order to be compatible with analog signals afterdigital-analog conversion of a quantized signal. In this case, there isa quantization error majored in modulus by${e_{\max} = \frac{1}{2 \times {Cq}}},$

[0015] where Cq is the corresponding quantization coefficient. However,it may arise that this resolution is insufficient for representing someor all of the digital signals of the system.

[0016] On the other hand, certain digital systems use constant digitalvalues. In a radio transmitter or receiver, for example, such a digitalconstant may represent the central frequency of a radio channel. In thiscase, the situation may be encountered in which a quantization erroraffecting the digital constant (this error being systematic inasmuch asit does not vary) exceeds the maximum tolerable error for digitalrepresentation of this constant. If the system does not dictate thequantization of the digital data, then the systematic quantization erroraffecting a specific digital constant K may be reduced, albeit this maymean that the dynamic range of the system is not optimized, by choosingthe quantization coefficient Cq such that${{K - \frac{{round}\left( {K \times {Cq}} \right)}{Cq}} \leq e_{d} \leq e_{\max}},$

[0017] where e_(d) is the maximum tolerable error for digitalrepresentation of the constant K. This is not always possible in asystem which dictates the quantization of the digital data, such as adigitally modulated frequency synthesizer, for example.

[0018] This is why it is a first object of the invention to reduce thequantization errors of a digital signal and/or to digitally correct asystematic quantization error of a digital value (in particular aconstant value) without any constraint governing the quantization, thatis to say without any constraint governing n and Cq.

[0019] It is moreover possible for digital data obtained from twosubsystems, having respective quantizations determined by distinctquantization coefficients, to be used in a digital system only if one ofthe two quantization coefficients is an integer multiple of the other.

[0020] Specifically, if data obtained from a first subsystem, having aquantization determined by a first coefficient Cq1, are intended to beused in the same digital system with digital data obtained from a secondsubsystem, having a quantization determined by a second coefficient Cq2different to Cq1, then Cq1 and/or Cq2 must be chosen such that Cq2=r×Cq1or Cq1=r×Cq2, where r is an integer.

[0021] The data can then be rendered uniform by multiplying the data ofthe first subsystem or of the second subsystem, as applicable, by r.This, however, is only possible if at least one of the subsystems doesnot dictate the quantization of the digital data.

[0022] This is why it is a second object of the invention to allow aplurality of digital systems to be connected together, while insuringcompatibility of the data but without any constraints governing theirrespective quantizations.

[0023] A first aspect of the invention thus provides a method forconverting a digital input value quantized according to a firstquantization coefficient and encoded over and most n1 bits, into adigital output value quantized according to a second quantizationcoefficient and encoded over at most n2 bits, where n1 and n2 arenonzero integers.

[0024] The method comprises the steps consisting in:

[0025] a) multiplying the digital input value by an integer B encodedover at most β bits, where β is a nonzero integer, in order to generatea first intermediate digital value encoded over at most n1+β bits; and

[0026] b) fixed-point dividing said first intermediate digital value bythe number 2^(α), where α is an integer less than or equal to n1+β, inorder to generate said digital output value.

[0027] According the invention, the number $\frac{B}{2^{\alpha}}$

[0028] is substantially equal to the ratio of said second quantizationcoefficient to said first quantization coefficient. Step b) isfurthermore carried out by means of a sigma-delta modulator (Σ−Δmodulator) . This is preferably a 1^(st) order Σ−Δ modulator, which isthe simplest to use.

[0029] It will be noted that digital/digital conversion is involved,that is to say both the digital output value and the digital input valueare quantized digital values. What changes is the quantization of thisdigital value. In particular, the Σ−Δ modulator is a digital/digitalmodulator.

[0030] A second aspect of the invention also provides a device forconverting a digital input value quantized according to a firstquantization coefficient and encoded over at most n1 bits, into adigital output value quantized according to a second quantizationcoefficient and encoded over at most n2 bits, where n1 and n2 arenonzero integers.

[0031] The device comprises multiplier means for multiplying the digitalinput value by an integer B encoded over at most β bits, where β is anonzero integer. These multiplier means generate a first intermediatedigital value encoded over at most n1+β bits. The device furthermorecomprises divider means for fixed-point dividing said first intermediatedigital value by the number 2α, where a is an integer less than or equalto n1+β. These divider means generate said digital output value.

[0032] According the invention, the number $\frac{B}{2^{\alpha}}$

[0033] is substantially equal to the ratio of said second quantizationcoefficient to said first quantization coefficient. Said divider meansfurthermore comprise a sigma-delta (Σ−Δ) modulator.

[0034] As is known, a Σ−Δ modulator is a circuit synchronous with thesampling frequency of the input signal. It performs quantization “noiseshaping” at the high frequencies. A signal with a reduced quantizationnoise at the useful frequencies is recovered at the output of the Σ−Δmodulator. On average, that is to say at a low frequency compared withthe sampling frequency, the gain of the device is equal to$\frac{B}{2^{\alpha}}.$

[0035] A digital output value which corresponds, with good precision, tothe digital input value multiplied by the ratio of said secondquantization coefficient to the first quantization coefficient istherefore obtained at the output of the Σ−Δ modulator.

[0036] The principle of the invention is based on the following concept.In what follows, Sq1 will denote the digital input value (quantizedinformation) and Cq1 will denote the first quantization coefficient.Likewise, Sq2 will denote the digital output value (quantizedinformation) and Cq2 will denote the second quantization coefficient.Lastly, S will denote the real value (unquantized information)corresponding to Sq1 and Sq2. The relations below are then written:$\begin{matrix}{{Sq2} = {{round}\quad \left( {S \cdot {Cq2}} \right)}} & (6) \\{{{whence}\quad {Sq2}} \cong {{round}\quad {\left( {S \cdot {Cq1}} \right) \cdot \frac{Cq2}{Cq1}}}} & (7) \\{{{whence}\quad {Sq2}} \cong {{Sq1} \cdot \frac{Cq2}{Cq1}}} & (8) \\{{{that}\quad {is}\quad {to}\quad {say}\quad {Sq2}} \cong {{Sq1} \cdot \frac{B}{2^{\alpha}}}} & (9) \\{{{with}\quad \frac{Cq2}{Cq1}} \cong \frac{B}{2^{\alpha}}} & (10)\end{matrix}$

[0037] It can be seen that the effect of the invention is to implementrelation (9) by using relation (10). It therefore makes it possible toconvert the digital value Sq1 into a digital value Sq2, which areinformation quantized according to different respective quantizationcoefficients Cq1 and Cq2 and which both correspond to the same realinformation S, without any restrictive assumption being made about therelation between one of these quantization coefficients and the other.

[0038] The invention thus makes it possible to reduce the quantizationerror affecting a variable or constant real value. Specifically, it issufficient to choose the first quantization coefficient Cq1 so as tominimize the quantization error affecting the digital value Sq1, and toconvert this value by delivering it as a digital input value to a deviceaccording to the invention, in order to obtain a digital output valueSq2 quantized according to a second quantization coefficient Cq2, whichwill be chosen as being that of the quantization of the subsystemneeding to use the digital input value. The quantization error affectingthe digital value Sq2 can thus be reduced without any constraintsgoverning the quantization of the subsystem.

[0039] This is shown by the following calculation of the quantizationerror e affecting the real value S, in the case when the deviceaccording to the invention is used.

[0040] The expression for e is given by: $\begin{matrix}{e = {S - \frac{\left( {{Sq1} \cdot \frac{B}{2^{\alpha}}} \right)}{Cq2}}} & (11)\end{matrix}$

[0041] But Sq1=round(S.Cq1).

[0042] Whence |Sq1|≦|S.Cq1|+½ and −Sq1≦−S.Cq1+½

[0043] From this it follows:$e \leq {S - \frac{\left( {S \cdot {Cq1} \cdot \frac{B}{2^{\alpha}}} \right)}{Cq2} + {\frac{1}{2} \cdot \frac{\left( \frac{B}{2^{\alpha}} \right)}{Cq2}}}$${{i.e.\quad {e}} \leq {{{S} \cdot {{1 - {\frac{Cq1}{Cq2} \cdot \frac{B}{2^{\alpha}}}}}} + {\frac{1}{2} \cdot \frac{\left( \frac{B}{2^{\alpha}} \right)}{Cq2}}}} = {{{S} \cdot {{1 - {\frac{Cq1}{Cq2} \cdot \frac{B}{2^{\alpha}}}}}} + {\frac{1}{2 \cdot {Cq1}} \cdot \left( {\frac{Cq1}{Cq2} \cdot \frac{B}{2^{\alpha}}} \right)}}$

[0044] The choice of B and α gives${{\frac{Cq1}{Cq2} \cdot \frac{B}{2^{\alpha}}} = {1 + ɛ}},$

[0045] where ε denotes a negligible quantity compared with unity(ε=o(1)). It then follows: $\begin{matrix}{{e} \leq {{{S} \cdot {ɛ}} + {\frac{1}{2 \cdot {Cq1}} \cdot \left( {1 + ɛ} \right)}} \cong {{{S} \cdot {ɛ}} + \frac{1}{2 \cdot {Cq1}}}} & (12)\end{matrix}$

[0046] The quantization error of the quantized value Sq2 obtained by themethod according to the invention is therefore at most equal to the sum,on the one hand, of the maximum quantization error of the value Sq1quantized according to the quantization coefficient Cq1 and, on theother hand, an image of the real value S which will in general benegligible. With a quantization according to the quantizationcoefficient Cq2, there would have been an error majored by$\frac{1}{2 \cdot {Cq2}}.$

[0047] In order to reduce the quantization error affecting the value ofSq2 in the subsystem that uses this value, the value of Cq1 willadvantageously be chosen such that Cq1 is greater than Cq2 (Cq1>Cq2).

[0048] In the particular case when the digital value in question is aninteger, the first digital input value Sq1 is equal to the real value S(Sq1=S) and the first quantization coefficient Cq1 is equal to unity(Cq1=1). The quantization error affecting Sq1 is then zero, and thequantization error affecting Sq2 is then minimal. In this case, relation(12) is written:

e=S×ε  (13)

[0049] The invention furthermore makes it possible for a digital valueSq1 of a first subsystem, having a first specific quantization, to beadapted to a second specific quantization which is associated with asecond subsystem that needs to use this digital value, without anyconstraints governing the respective quantizations of these twosubsystems. Specifically, it is sufficient to deliver this digital valueSq1 as a digital input value to a device according to the invention, inwhich said first quantization coefficient Cq1 is chosen to be equal tothat of said first specific quantization, and in which said secondquantization coefficient Cq2 is chosen to be equal to that of saidsecond specific quantization.

[0050] A third aspect of the invention provides a digitally modulatedfrequency synthesizer, comprising a phase-locked loop comprising avariable-ratio frequency divider in the return path. The division ratioof said divider is controlled by a digital value obtained in particularfrom a real value corresponding to the central frequency of a radiochannel. The synthesizer furthermore comprises a conversion device asdefined, for reducing the quantization error affecting said real value.

[0051] Other characteristics and advantages of the invention willmoreover become apparent on reading the description which follows. Thisdescription is purely illustrative and should be read with reference tothe appended drawings, in which:

[0052]FIG. 1 is a block diagram of a device according to the invention;

[0053]FIG. 2 is a flow chart of the steps in a method according to theinvention;

[0054]FIG. 3 is a block diagram of a first embodiment of the device inFIG. 1;

[0055]FIG. 4 is a block diagram of a second embodiment of the device inFIG. 1;

[0056]FIG. 5 is a diagram illustrating the application of a mask to aspecific digital value;

[0057]FIG. 6 is a block diagram of a third embodiment of the device inFIG. 1; and

[0058]FIG. 7 is a block diagram of a digitally modulated synthesizerincorporating a device according to the invention.

[0059]FIG. 1 represents the block diagram of a device according to theinvention.

[0060] The device comprises an input 1 for receiving a digital inputvalue Sq1, which is a quantized value of a variable or constant realvalue. The value Sq1 is quantized according to a first quantizationcoefficient Cq1 and encoded over at most n1 bits, where n1 is a nonzerointeger. The device also comprises an output 2 for delivering a digitaloutput value Sq2. The value Sq2 is quantized according to a secondquantization coefficient Cq2 and encoded over at most n2 bits, where n2is a nonzero integer.

[0061] The device also comprises means, such as a digital multiplier 10,for multiplying the digital input value Sq1 by an integer B encoded overat most β bits, where β is a nonzero integer. The means 10 generate afirst intermediate digital value C encoded over at most n1+β bits.

[0062] The device further comprises divider means for fixed-pointdividing said first intermediate digital value C by the number 2^(α),where α is an integer less than or equal to n1+β. These divider meansgenerate the digital output value Sq2.

[0063] According to the invention, these divider means comprise asigma-delta modulator 20, which receives the intermediate value C asinput and delivers the digital output value Sq2 as output. The Σ−Δmodulator is a digital/digital modulator, which receives as input adigital value encoded over n1+β bits and delivers as output a digitalvalue encoded over n1+β+1−α bits. It is preferably a 1^(st) order Σ−Δ,modulator, which is the simplest to use. Embodiments with a higher-orderΣ−Δ modulator may nevertheless be envisaged.

[0064] According to the invention, the number $\frac{B}{2^{\alpha}}$

[0065] is furthermore substantially equal to the ratio $\frac{Cq2}{Cq1}$

[0066] of the second quantization coefficient Cq2 to the firstquantization coefficient Cq1.

[0067] As mentioned in the introduction, such a device converts thedigital value Sq1, quantized according to the quantization coefficientCq1, into the digital value Sq2, quantized according to the quantizationcoefficient Cq2.

[0068]FIG. 2 is a flow chart illustrating the steps in a methodaccording to the invention. The method is carried out by a device asdescribed above with reference to FIG. 1.

[0069] In a step 100, the digital input value Sq1 is received.

[0070] In a step 200, the value Sq1 is multiplied by the number B inorder to generate the first intermediate digital value C.

[0071] In a step 300, the first intermediate digital value C isfixed-point divided by the number 2^(α) in order to generate the digitaloutput value Sq2. According to the invention, step 300 is carried out bymeans of a sigma-delta modulator. The number $\frac{B}{2^{\alpha}}$

[0072] is furthermore substantially equal to the ratio$\frac{Cq2}{Cq1}.$

[0073] The diagram in FIG. 3 illustrates a first embodiment of a deviceaccording to the invention, which is suitable for carrying out a firstvariant of the method.

[0074] In this first embodiment, the sigma-delta modulator 20 comprisesmeans 21 such as a digital adder, which receive as input the firstintermediate digital value C as a first operand, on the one hand, and adigital error value E as a second operand, on the other hand. The latteris encoded over at most α bits. The means 21 deliver as output a secondintermediate digital value D encoded over at most n1+β+1 bits.

[0075] The device further comprises selection means 23, such as adigital discriminator, for selecting the n2 most significant bits of thesecond intermediate digital value D as the digital output value Sq2, andfor selecting the α least significant bits of said second intermediatedigital value D as the digital error value E. It follows that n2 isequal to n1+β+1−α. The means 23 receive the value D as input and deliverthe value Sq2 as well as the value E as output.

[0076] A digital discriminator is a circuit which separates the khigh-significance bits and the j low-significance bits of a givendigital input value in order to generate two digital output values,encoded respectively over k bits and over j bits and each having as itsvalue the value corresponding respectively to said k high-significancebits and to the j low-significance bits. Here, the discriminator 23separates the n1+β+1−α most significant bits of the second intermediatedigital value D, on the one hand, and the α least significant bits ofthe value D, on the other hand.

[0077] The diagram in FIG. 4 illustrates a second embodiment of a deviceaccording to the invention, which is suitable for carrying out a secondvariant of the method.

[0078] In this second embodiment, the selection means 23 of the devicecomprise an operator 24 for shifting to the right by α bits. Such anoperator is formed, for example, with the aid of a properly controlledshift register. This operator 24 receives as input the n1+β+1 bits ofthe second intermediate digital value D. It delivers as output then1+β+1−α most significant bits of the second intermediate digital valueD as a digital output value Sq2.

[0079] The selection means 23 furthermore comprise means 25 for applyinga mask to the second intermediate digital value D.

[0080] Such a mask is represented in FIG. 5 with the reference M. It isa digital value stored in an appropriate register and having at mostn1+β+1 bits, the n1+β+1−α most significant bits of which are equal tothe logical value 0 and the α least significant bits of which are equalto the logical value 1. When it is combined with the second intermediatedigital value D in an operation of the logical AND type, it makes itpossible to select the α least significant bits of said secondintermediate digital value D.

[0081] Stated otherwise, the means 25 receive as input the n1+β+1 bitsof the second intermediate digital value D. They deliver as output then1+β+1−α most significant bits of the second intermediate digital valueD as the digital error value E.

[0082] The diagram in FIG. 6 illustrates a third embodiment of a deviceaccording to the invention, which is suitable for carrying out a thirdvariant of the method.

[0083] In this third embodiment, the selection means 23 of the devicestill comprise an operator 24 for shifting to the right by a bits, whichhas the same function as the operator 24 of the device in FIG. 4.

[0084] The selection means 23 further comprise an operator 26 forshifting to the left by α bits, which receives as input the n1+β+1−αbits of the digital output value Sq2 and delivers as output a thirdintermediate digital value F, encoded over at most n1+β+1 bits. Theoperator 26 is, for example, a properly controlled shift register. Theyfurthermore comprise an operator 27 for taking the difference betweenthe intermediate digital values F and C. The operator 27 is, forexample, a digital subtracter. It receives the third intermediatedigital value F as a first operand, and the first intermediate digitalvalue C as a second operand. It delivers as output the digital errorvalue E.

[0085] In each of the three embodiments described above with referenceto FIGS. 3, 4 and 6, the device preferably comprises an operator 22 thatapplies a unitary delay to the digital error value E for synchronizationreasons. Stated otherwise, the error signal E is delivered to the inputof the adder means 21 through a unitary delay operator 22.

[0086]FIG. 6 shows the diagram of a digitally modulated frequencysynthesizer, more commonly referred to by the term DMS, whichincorporates a device according to the invention.

[0087] Such a circuit can be used for generating a frequency- orphase-modulated radiofrequency signal (in the UHF band lying between 400and 600 MHz). Applications may be found for it in the radio transmittersor transceivers of a radiocommunication system, particularly in the basestations and/or the mobile terminals of such a system.

[0088] A DMS has a structure which is derived from the structure of afractional N frequency synthesizer, and makes it possible to generate afrequency- or phase-modulated periodic signal.

[0089] The DMS includes a phase-locked loop or “PLL”, comprising aphrase/frequency comparator 11 or “PFC”, a loop filter 12 such as anintegrator, and a voltage controlled oscillator 13 or “VCO” in series ina forward channel, and as well as a frequency divider 14 in a returnchannel. The VCO delivers as output a signal S_(out) which is the outputsignal of the DMS, the instantaneous frequency of which is f_(out). ThePFC receives at a first input a reference signal S_(ref) having areference frequency f_(ref), and at a second input a signal S_(div)delivered by the frequency divider 14 on the basis of the signalS_(out).

[0090] For conventional fractional N synthesis, the frequency divider 14is a variable-ratio divider making it possible to produce the signalS_(div) by dividing the frequency f_(out) of the signal S_(out) by adivision ratio, which alternately has the value of an integer N for apart of the time T1 and the integer N+1 for the rest of the time T2. Inthis way, the frequency f_(out) of the output signal S_(out) is given asa function of the frequency f_(ref) of the reference signal S_(ref) by:$\begin{matrix}{f_{out} = {\left( {N + \frac{T1}{{T1} + {T2}}} \right) \times f_{ref}}} & (14)\end{matrix}$

[0091] In a digitally modulated synthesizer, the frequency divider 14includes an input for controlling the division ratio. This ratio isfixed by the value stored in a specific accumulator. In order to preventspurious lines, due to periodicity of the division ratio changes from Nto N+1 and back again, from occurring in the spectrum of the outputsignal Soutt however, a DMS known in the prior art furthermore includesa modulator 15 of the digital/digital Σ−Δ modulator type.

[0092] The modulator 15 includes an input which receives a digitalfrequency- or phase-modulation value S_(mod) encoded over k bits, and anoutput which delivers a digital value S′_(mod), corresponding to theprocessed value S_(mod) and encoded over j bits. The output of themodulator 15 is connected to a first input of a digital adder 16, thesecond input of which receives a digital value N_(o) that defines thebottom of the frequency band addressed by the synthesizer. The output ofthe adder 16 delivers a digital value S_(c). It is connected to thecontrol input of the divider 14 in order to deliver the value S_(c) toit.

[0093] The DMS also comprises a second digital adder 17, a first inputof which receives a digital value S_(info) and a second input of whichreceives a digital value S_(ch2). The output of the adder 17 deliversthe aforementioned digital frequency- or phase-modulation value S_(mod).The digital value S_(info) contains the modulation information(modulating signal), that is to say the useful information to betransmitted. The digital value S_(ch2) corresponds to the centralfrequency of the radio channel (after the aforementioned value N_(o) hasbeen added).

[0094] The digital values S_(info), S_(ch2), S_(mod) and S′_(mod) andN_(o) are values that are quantized according to a quantizationcoefficient Cq2 of the digital system constituted by the DMS.

[0095] According to the invention, the value S_(ch2) is delivered by aconverter device 18 as described above with reference to FIGS. 2 to 6,on the basis of a digital value S_(chq1) stored in an appropriateregister. The quantized values S_(ch1), and S_(ch2) correspond to a realvalue, namely the central frequency of the channel, denoted below byF_(ch). The real value F_(ch) is constant, because the central frequencyof the channel is constant. If the device 18 was not there, the realvalue F_(ch) would be directly quantized according to the quantizationcoefficient Cq2 of the digital system constituted by the DMS. However,the DMS presented here incorporates a device 18 according to theinvention in order to reduce the quantization error affecting thequantized digital value corresponding to the real value F_(ch) (which isa systematic error since this value is constant). Stated otherwise, theDMS comprises a device 18 for converting the digital value S_(ch1) intoa digital value S_(ch2), which is quantized according to thequantization coefficient Cq2 of the digital system constituted by theDMS.

[0096] To apply that which has been described above, a choice istherefore made to implement a converter device 18 of the type describedabove, for which Cq1 is equal to unity (Cq1=1, because the real valueF_(ch) is integer) and for which Cq2 is the quantization coefficient ofthe quantization of the DMS.

[0097] A numerical example for illustrating the advantages offered bythe invention in this application will be given below. In this example:

[0098] F_(ref)=9.6 MHz (megahertz);

[0099] k=22;

[0100] j=4;

[0101] F_(ch)=400017.5 kHz (kilohertz);

[0102] N_(o)=round(395 MHz/F_(ref));

[0103] e_(d)=4 Hz (hertz).

[0104] The frequency resolution of such a DMS is given by$\frac{F_{ref}}{2^{k - j}},$

[0105] where k is the number of bits at the input of the sigma-deltamodulator 15, and where j is the number of bits at the output of thismodulator. The frequency resolution of the DMS, that is to say$\frac{1}{Cq2},$

[0106] is therefore:$\frac{1}{Cq2} = {\frac{F_{ref}}{2^{k - j}} = {\frac{9.6 \cdot 10^{6}}{2^{18}} \approx {36.62\quad {Hz}}}}$

[0107] The value F_(min), corresponding to the bottom of the frequencyband addressed by the DMS, is determined by the digital value N_(o)according to the relation F_(min)=N_(o)×F_(ref). Here, therefore,F_(min)=41×9.6·10⁶=393.6 MHz.

[0108] Let us first consider what the situation would be without thedevice 18 according to the invention, that is to say if Sch1=Sch2. Wewould have:

Fch2=round[(F _(ch) −F _(min)).Cq2]=175241

[0109] The systematic quantization error affecting the central frequencyof the radio channel would therefore be:$e = {F_{ch} - \left( {\frac{Fch2}{Cq2} + F_{\min}} \right)}$

[0110] i.e.:$e = {{{400017.5 \cdot 10^{3}} - \left( {\frac{175241}{Cq2} + {393.6 \cdot 10^{6}}} \right)} = {{- 17.08}\quad {Hz}}}$

[0111] This value exceeds (in absolute value) the acceptable errore_(d).

[0112] Let us now consider what happens with the conversion device 18according to the invention. Since the signal intended to be representedis integer, we have Cq1=1.

[0113] The following approximation is chosen:${{Cq2} \approx \frac{B}{2^{\alpha}}} = {\frac{229065}{2^{23}}.}$

[0114] In other words, a choice is made to implement a device accordingto the invention with B=229065 and α=23.

[0115] The quantization error can be determined by using the relation(13) given in the introduction, which is valid in the case when the realdigital value at the input of the device (here, the constant valueF_(ch)−F_(min)) is an integer. It will be recalled that this relation isthen written:$e = {{S \cdot ɛ} = {{{S \cdot \frac{Cq1}{Cq2}}\quad \frac{B}{2^{\alpha}}1} \cong {2.17\quad {Hz}}}}$

[0116] where S denotes the real digital value at the input of the device(here F_(ch)).

[0117] Whence it follows that e≅2.17 Hz. The goal of a quantizationerror less than 4 Hz affecting the value of the central frequency of theradio channel has therefore indeed been achieved, without having tomodify the quantization of the system. Here, the invention makes itpossible to reduce the systematic quantization error affecting the valueof the central frequency of the radio channel from 17 Hz to 2 Hz.

[0118] A better result could be obtained by increasing the precision ofthe approximation for $\frac{Cq2}{Cq1},$

[0119] but at the cost of increasing the number β and the number α.

1. A method for converting a digital input value quantized according toa first quantization coefficient and encoded over and most n1 bits, intoa digital output value quantized according to a second quantizationcoefficient and encoded over and most n2 bits, where n1 and n2 arenonzero integers, comprising the steps of: multiplying the digital inputvalue by an integer B encoded over at most β bits, where β is a nonzerointeger, so as to generate a first intermediate digital value encodedover at most n1+β bits; and fixed-point dividing said first intermediatedigital value by the number 2^(α), where α is an integer less than orequal to n1+β, in order so as to generate said digital output value,wherein the number $\frac{B}{2^{\alpha}}$

is substantially equal to the ratio of said second quantizationcoefficient to said first quantization coefficient; and wherein the stepof fixed point dividing is carried out by means of a sigma-deltamodulator.
 2. The method as claimed in claim 1, wherein the step offixed-point dividing comprises the steps of: adding said firstintermediate digital value, on the one hand, and a digital error valueencoded over at most α bits, on the other hand, so as to generate asecond intermediate digital value encoded over at most n1+β+1 bits;selecting a given number n2 of the most significant bits of said secondintermediate digital value as the digital output value, where n2 isequal to n1+β+1−α; and selecting a given number α of the leastsignificant bits of said second intermediate digital value as thedigital error value.
 3. The method as claimed in claim 2, wherein thesteps of selecting are carried out together with the aid of adiscriminator for separating the n1+β+1−α most significant bits of thesecond intermediate digital value, on the one hand, and the α leastsignificant bits of said second intermediate digital value, on the otherhand.
 4. The method as claimed in claim 2, wherein the step of selectingthe n2 most significant bits is carried out via an operation of shiftingto the right by α bits, which is applied to the n1+β+1 bits of thesecond intermediate digital value.
 5. The method as claimed in claim 4,wherein the step of selecting the α least significant bits is carriedout by applying to the second intermediate digital value a mask havingat most n1+β+1 bits, the n1+α+1−α most significant bits of which areequal to the logical value 0 and the α least significant bits of whichare equal to the logical value
 1. 6. The method as claimed in claim 4,wherein the step of selecting the α least significant bits is carriedout, on the one hand, by an operation of shifting to the left by α,which is applied to the n1+β+1−α bits of the digital output value forgenerating a third intermediate digital value encoded over at mostn1+β+1 bits and, on the other hand, by a difference operation betweensaid third intermediate digital value and said teast intermediatedigital value.
 7. The method as claimed in claim 1, wherein neither thefirst quantization coefficient nor the second quantization coefficientis an integer multiple of the other.
 8. A device for converting adigital input value quantized according to a first quantizationcoefficient and encoded over at most n1 bits, into a digital outputvalue quantized according to a second quantization coefficient andencoded over at most n2 bits, where n1 and n2 are nonzero integers,comprising: multiplier means for multiplying the digital input value byan integer B encoded over at most β bits, where β is a nonzero integer,so as to generate a first intermediate digital value encoded over atmost n1+β bits; ad divider means for fixed-point dividing said firstintermediate digital value by the number 2^(α), where α is an integerless than or equal to n1+β, so as to generate said digital output value,wherein the number $\frac{B}{2^{\alpha}}$

is substantially equal to the ratio of said second quantizationcoefficient to said first quantization coefficient; and wherein saiddivider means comprise a sigma-delta modulator.
 9. The device as claimedin claim 8, wherein the sigma-delta modulator is a 1^(st) order tosigma-delta modulator.
 10. The device as claimed in claim 9, wherein thesigma-delta modulator comprises: adder means which receive as input saidfirst intermediate digital value as a first operand, on the one hand,and a digital error value encoded over at most α bits as a secondoperand, on the other hand, and which deliver as output a secondintermediate digital value encoded over at most n1+β+1 bits; selectionmeans for selecting a given number n2 of the most significant bits ofsaid second intermediate digital value as the digital output value,where n2 is equal to n1+β+1−α; and for selecting the [[α]] a givennumber α of the least significant bits of said second intermediatedigital value as the digital error value.
 11. The device as claimed inclaim 10, wherein said selection means comprise a discriminator forseparating the n1+β+1−α most significant bits of the second intermediatedigital value, on the one hand, and the α least significant bits of saidsecond intermediate digital value, on the other hand.
 12. The device asclaimed in claim 10, wherein said selection means comprise an operatorfor shifting to the right by α bits, which receives as input the n1+β+1bits of the second intermediate digital value, and which delivers asoutput the n1+β+1−α most significant bits of the second intermediatedigital value as a digital output value.
 13. The device as claimed inclaim 12, wherein said selection means further comprise means forapplying to the second intermediate digital value a mask having at mostn1+β+1 bits, the n1+β+1−α most significant bits of which are equal tothe logical value 0 and the α least significant bits of which are equalto the logical value 1, so as to select the oa least significant bits ofsaid second intermediate digital value as the digital error value. 14.The device as claimed in claim 12, wherein said selection means furthercomprise, on the one hand, an operator for shifting to the left by αbits, which receives as input the n1+β+1−α bits of the digital outputvalue and delivers as output a third intermediate digital value encodedover at most n1+β+1 bits and, on the other hand, a difference operatorwhich receives said third intermediate digital value as a first operandand said first intermediate digital value as a second operand, and whichdelivers as output the digital error value.
 15. The device as claimed inclaim 1, wherein the error signal is delivered to the input of the addermeans through a unitary delay operator.
 16. A digitally modulatedfrequency synthesizer, comprising a phase-locked loop comprising avariable-ratio frequency divider in the return path, wherein thedivision ratio is controlled by a digital value obtained in particularfrom a real value [[(F_(ch))]] corresponding to the central frequency ofa radio channel, the synthesizer further comprising a conversion deviceas claimed in claim 8 for reducing the quantization error affecting saidreal value.